// SPDX-License-Identifier: BSD-2-Clause-Views
/*
 * Copyright (c) 2022-2023 The Regents of the University of California
 */

#ifndef XCVR_GTYE4_H
#define XCVR_GTYE4_H

#include "xcvr_gt.h"
#include "gt/gtye4_regs.h"

// signals
#define GTYE4_COM_QPLL0_RESET_ADDR 0x10000
#define GTYE4_COM_QPLL0_RESET_MSB 0
#define GTYE4_COM_QPLL0_RESET_LSB 0
#define GTYE4_COM_QPLL0_RESET_MASK BIT_MASK(GTYE4_COM_QPLL0_RESET_MSB, GTYE4_COM_QPLL0_RESET_LSB)
#define GTYE4_COM_QPLL0_LOCK_ADDR 0x10000
#define GTYE4_COM_QPLL0_LOCK_MSB 8
#define GTYE4_COM_QPLL0_LOCK_LSB 8
#define GTYE4_COM_QPLL0_LOCK_MASK BIT_MASK(GTYE4_COM_QPLL0_LOCK_MSB, GTYE4_COM_QPLL0_LOCK_LSB)
#define GTYE4_COM_QPLL0_PD_ADDR 0x10001
#define GTYE4_COM_QPLL0_PD_MSB 0
#define GTYE4_COM_QPLL0_PD_LSB 0
#define GTYE4_COM_QPLL0_PD_MASK BIT_MASK(GTYE4_COM_QPLL0_PD_MSB, GTYE4_COM_QPLL0_PD_LSB)
#define GTYE4_COM_QPLL1_RESET_ADDR 0x11000
#define GTYE4_COM_QPLL1_RESET_MSB 0
#define GTYE4_COM_QPLL1_RESET_LSB 0
#define GTYE4_COM_QPLL1_RESET_MASK BIT_MASK(GTYE4_COM_QPLL0_RESET_MSB, GTYE4_COM_QPLL0_RESET_LSB)
#define GTYE4_COM_QPLL1_LOCK_ADDR 0x11000
#define GTYE4_COM_QPLL1_LOCK_MSB 8
#define GTYE4_COM_QPLL1_LOCK_LSB 8
#define GTYE4_COM_QPLL1_LOCK_MASK BIT_MASK(GTYE4_COM_QPLL0_LOCK_MSB, GTYE4_COM_QPLL0_LOCK_LSB)
#define GTYE4_COM_QPLL1_PD_ADDR 0x11001
#define GTYE4_COM_QPLL1_PD_MSB 0
#define GTYE4_COM_QPLL1_PD_LSB 0
#define GTYE4_COM_QPLL1_PD_MASK BIT_MASK(GTYE4_COM_QPLL1_PD_MSB, GTYE4_COM_QPLL1_PD_LSB)

#define GTYE4_CH_TX_RESET_ADDR 0x10000
#define GTYE4_CH_TX_RESET_MSB 0
#define GTYE4_CH_TX_RESET_LSB 0
#define GTYE4_CH_TX_RESET_MASK BIT_MASK(GTYE4_CH_TX_RESET_MSB, GTYE4_CH_TX_RESET_LSB)
#define GTYE4_CH_TX_PMA_RESET_ADDR 0x10000
#define GTYE4_CH_TX_PMA_RESET_MSB 1
#define GTYE4_CH_TX_PMA_RESET_LSB 1
#define GTYE4_CH_TX_PMA_RESET_MASK BIT_MASK(GTYE4_CH_TX_PMA_RESET_MSB, GTYE4_CH_TX_PMA_RESET_LSB)
#define GTYE4_CH_TX_PCS_RESET_ADDR 0x10000
#define GTYE4_CH_TX_PCS_RESET_MSB 2
#define GTYE4_CH_TX_PCS_RESET_LSB 2
#define GTYE4_CH_TX_PCS_RESET_MASK BIT_MASK(GTYE4_CH_TX_PCS_RESET_MSB, GTYE4_CH_TX_PCS_RESET_LSB)
#define GTYE4_CH_TX_RESET_DONE_ADDR 0x10000
#define GTYE4_CH_TX_RESET_DONE_MSB 8
#define GTYE4_CH_TX_RESET_DONE_LSB 8
#define GTYE4_CH_TX_RESET_DONE_MASK BIT_MASK(GTYE4_CH_TX_RESET_DONE_MSB, GTYE4_CH_TX_RESET_DONE_LSB)
#define GTYE4_CH_TX_GT_RESET_DONE_ADDR 0x10000
#define GTYE4_CH_TX_GT_RESET_DONE_MSB 9
#define GTYE4_CH_TX_GT_RESET_DONE_LSB 9
#define GTYE4_CH_TX_GT_RESET_DONE_MASK BIT_MASK(GTYE4_CH_TX_GT_RESET_DONE_MSB, GTYE4_CH_TX_GT_RESET_DONE_LSB)
#define GTYE4_CH_TX_PMA_RESET_DONE_ADDR 0x10000
#define GTYE4_CH_TX_PMA_RESET_DONE_MSB 10
#define GTYE4_CH_TX_PMA_RESET_DONE_LSB 10
#define GTYE4_CH_TX_PMA_RESET_DONE_MASK BIT_MASK(GTYE4_CH_TX_PMA_RESET_DONE_MSB, GTYE4_CH_TX_PMA_RESET_DONE_LSB)
#define GTYE4_CH_TX_PRGDIV_RESET_DONE_ADDR 0x10000
#define GTYE4_CH_TX_PRGDIV_RESET_DONE_MSB 11
#define GTYE4_CH_TX_PRGDIV_RESET_DONE_LSB 11
#define GTYE4_CH_TX_PRGDIV_RESET_DONE_MASK BIT_MASK(GTYE4_CH_TX_PRGDIV_RESET_DONE_MSB, GTYE4_CH_TX_PRGDIV_RESET_DONE_LSB)
#define GTYE4_CH_TX_USRCLK_ACT_ADDR 0x10000
#define GTYE4_CH_TX_USRCLK_ACT_MSB 12
#define GTYE4_CH_TX_USRCLK_ACT_LSB 12
#define GTYE4_CH_TX_USRCLK_ACT_MASK BIT_MASK(GTYE4_CH_TX_USRCLK_ACT_MSB, GTYE4_CH_TX_USRCLK_ACT_LSB)
#define GTYE4_CH_TX_PD_ADDR 0x10001
#define GTYE4_CH_TX_PD_MSB 0
#define GTYE4_CH_TX_PD_LSB 0
#define GTYE4_CH_TX_PD_MASK BIT_MASK(GTYE4_CH_TX_PD_MSB, GTYE4_CH_TX_PD_LSB)
#define GTYE4_CH_TX_QPLL_SEL_ADDR 0x10001
#define GTYE4_CH_TX_QPLL_SEL_MSB 1
#define GTYE4_CH_TX_QPLL_SEL_LSB 1
#define GTYE4_CH_TX_QPLL_SEL_MASK BIT_MASK(GTYE4_CH_TX_QPLL_SEL_MSB, GTYE4_CH_TX_QPLL_SEL_LSB)
#define GTYE4_CH_TX_POLARITY_ADDR 0x10010
#define GTYE4_CH_TX_POLARITY_MSB 0
#define GTYE4_CH_TX_POLARITY_LSB 0
#define GTYE4_CH_TX_POLARITY_MASK BIT_MASK(GTYE4_CH_TX_POLARITY_MSB, GTYE4_CH_TX_POLARITY_LSB)
#define GTYE4_CH_TX_ELECIDLE_ADDR 0x10010
#define GTYE4_CH_TX_ELECIDLE_MSB 1
#define GTYE4_CH_TX_ELECIDLE_LSB 1
#define GTYE4_CH_TX_ELECIDLE_MASK BIT_MASK(GTYE4_CH_TX_ELECIDLE_MSB, GTYE4_CH_TX_ELECIDLE_LSB)
#define GTYE4_CH_TX_INHIBIT_ADDR 0x10010
#define GTYE4_CH_TX_INHIBIT_MSB 2
#define GTYE4_CH_TX_INHIBIT_LSB 2
#define GTYE4_CH_TX_INHIBIT_MASK BIT_MASK(GTYE4_CH_TX_INHIBIT_MSB, GTYE4_CH_TX_INHIBIT_LSB)
#define GTYE4_CH_TX_DIFFCTRL_ADDR 0x10011
#define GTYE4_CH_TX_DIFFCTRL_MSB 4
#define GTYE4_CH_TX_DIFFCTRL_LSB 0
#define GTYE4_CH_TX_DIFFCTRL_MASK BIT_MASK(GTYE4_CH_TX_DIFFCTRL_MSB, GTYE4_CH_TX_DIFFCTRL_LSB)
#define GTYE4_CH_TX_MAINCURSOR_ADDR 0x10012
#define GTYE4_CH_TX_MAINCURSOR_MSB 6
#define GTYE4_CH_TX_MAINCURSOR_LSB 0
#define GTYE4_CH_TX_MAINCURSOR_MASK BIT_MASK(GTYE4_CH_TX_MAINCURSOR_MSB, GTYE4_CH_TX_MAINCURSOR_LSB)
#define GTYE4_CH_TX_PRECURSOR_ADDR 0x10013
#define GTYE4_CH_TX_PRECURSOR_MSB 4
#define GTYE4_CH_TX_PRECURSOR_LSB 0
#define GTYE4_CH_TX_PRECURSOR_MASK BIT_MASK(GTYE4_CH_TX_PRECURSOR_MSB, GTYE4_CH_TX_PRECURSOR_LSB)
#define GTYE4_CH_TX_POSTCURSOR_ADDR 0x10014
#define GTYE4_CH_TX_POSTCURSOR_MSB 4
#define GTYE4_CH_TX_POSTCURSOR_LSB 0
#define GTYE4_CH_TX_POSTCURSOR_MASK BIT_MASK(GTYE4_CH_TX_POSTCURSOR_MSB, GTYE4_CH_TX_POSTCURSOR_LSB)
#define GTYE4_CH_TX_PRBS_SEL_ADDR 0x10040
#define GTYE4_CH_TX_PRBS_SEL_MSB 3
#define GTYE4_CH_TX_PRBS_SEL_LSB 0
#define GTYE4_CH_TX_PRBS_SEL_MASK BIT_MASK(GTYE4_CH_TX_PRBS_SEL_MSB, GTYE4_CH_TX_PRBS_SEL_LSB)
#define GTYE4_CH_TX_PRBS_FORCERR_ADDR 0x10040
#define GTYE4_CH_TX_PRBS_FORCERR_MSB 15
#define GTYE4_CH_TX_PRBS_FORCERR_LSB 0
#define GTYE4_CH_TX_PRBS_FORCERR_MASK BIT_MASK(GTYE4_CH_TX_PRBS_FORCERR_MSB, GTYE4_CH_TX_PRBS_FORCERR_LSB)
#define GTYE4_CH_RX_RESET_ADDR 0x11000
#define GTYE4_CH_RX_RESET_MSB 0
#define GTYE4_CH_RX_RESET_LSB 0
#define GTYE4_CH_RX_RESET_MASK BIT_MASK(GTYE4_CH_RX_RESET_MSB, GTYE4_CH_RX_RESET_LSB)
#define GTYE4_CH_RX_PMA_RESET_ADDR 0x11000
#define GTYE4_CH_RX_PMA_RESET_MSB 1
#define GTYE4_CH_RX_PMA_RESET_LSB 1
#define GTYE4_CH_RX_PMA_RESET_MASK BIT_MASK(GTYE4_CH_RX_PMA_RESET_MSB, GTYE4_CH_RX_PMA_RESET_LSB)
#define GTYE4_CH_RX_PCS_RESET_ADDR 0x11000
#define GTYE4_CH_RX_PCS_RESET_MSB 2
#define GTYE4_CH_RX_PCS_RESET_LSB 2
#define GTYE4_CH_RX_PCS_RESET_MASK BIT_MASK(GTYE4_CH_RX_PCS_RESET_MSB, GTYE4_CH_RX_PCS_RESET_LSB)
#define GTYE4_CH_RX_DFE_LPM_RESET_ADDR 0x11000
#define GTYE4_CH_RX_DFE_LPM_RESET_MSB 3
#define GTYE4_CH_RX_DFE_LPM_RESET_LSB 3
#define GTYE4_CH_RX_DFE_LPM_RESET_MASK BIT_MASK(GTYE4_CH_RX_DFE_LPM_RESET_MSB, GTYE4_CH_RX_DFE_LPM_RESET_LSB)
#define GTYE4_CH_EYESCAN_RESET_ADDR 0x11000
#define GTYE4_CH_EYESCAN_RESET_MSB 4
#define GTYE4_CH_EYESCAN_RESET_LSB 4
#define GTYE4_CH_EYESCAN_RESET_MASK BIT_MASK(GTYE4_CH_EYESCAN_RESET_MSB, GTYE4_CH_EYESCAN_RESET_LSB)
#define GTYE4_CH_RX_RESET_DONE_ADDR 0x11000
#define GTYE4_CH_RX_RESET_DONE_MSB 8
#define GTYE4_CH_RX_RESET_DONE_LSB 8
#define GTYE4_CH_RX_RESET_DONE_MASK BIT_MASK(GTYE4_CH_RX_RESET_DONE_MSB, GTYE4_CH_RX_RESET_DONE_LSB)
#define GTYE4_CH_RX_GT_RESET_DONE_ADDR 0x11000
#define GTYE4_CH_RX_GT_RESET_DONE_MSB 9
#define GTYE4_CH_RX_GT_RESET_DONE_LSB 9
#define GTYE4_CH_RX_GT_RESET_DONE_MASK BIT_MASK(GTYE4_CH_RX_GT_RESET_DONE_MSB, GTYE4_CH_RX_GT_RESET_DONE_LSB)
#define GTYE4_CH_RX_PMA_RESET_DONE_ADDR 0x11000
#define GTYE4_CH_RX_PMA_RESET_DONE_MSB 10
#define GTYE4_CH_RX_PMA_RESET_DONE_LSB 10
#define GTYE4_CH_RX_PMA_RESET_DONE_MASK BIT_MASK(GTYE4_CH_RX_PMA_RESET_DONE_MSB, GTYE4_CH_RX_PMA_RESET_DONE_LSB)
#define GTYE4_CH_RX_PRGDIV_RESET_DONE_ADDR 0x11000
#define GTYE4_CH_RX_PRGDIV_RESET_DONE_MSB 11
#define GTYE4_CH_RX_PRGDIV_RESET_DONE_LSB 11
#define GTYE4_CH_RX_PRGDIV_RESET_DONE_MASK BIT_MASK(GTYE4_CH_RX_PRGDIV_RESET_DONE_MSB, GTYE4_CH_RX_PRGDIV_RESET_DONE_LSB)
#define GTYE4_CH_RX_USRCLK_ACT_ADDR 0x11000
#define GTYE4_CH_RX_USRCLK_ACT_MSB 12
#define GTYE4_CH_RX_USRCLK_ACT_LSB 12
#define GTYE4_CH_RX_USRCLK_ACT_MASK BIT_MASK(GTYE4_CH_RX_USRCLK_ACT_MSB, GTYE4_CH_RX_USRCLK_ACT_LSB)
#define GTYE4_CH_RX_PD_ADDR 0x11001
#define GTYE4_CH_RX_PD_MSB 0
#define GTYE4_CH_RX_PD_LSB 0
#define GTYE4_CH_RX_PD_MASK BIT_MASK(GTYE4_CH_RX_PD_MSB, GTYE4_CH_RX_PD_LSB)
#define GTYE4_CH_RX_QPLL_SEL_ADDR 0x11001
#define GTYE4_CH_RX_QPLL_SEL_MSB 1
#define GTYE4_CH_RX_QPLL_SEL_LSB 1
#define GTYE4_CH_RX_QPLL_SEL_MASK BIT_MASK(GTYE4_CH_RX_QPLL_SEL_MSB, GTYE4_CH_RX_QPLL_SEL_LSB)
#define GTYE4_CH_LOOPBACK_ADDR 0x11002
#define GTYE4_CH_LOOPBACK_MSB 2
#define GTYE4_CH_LOOPBACK_LSB 0
#define GTYE4_CH_LOOPBACK_MASK BIT_MASK(GTYE4_CH_LOOPBACK_MSB, GTYE4_CH_LOOPBACK_LSB)
#define GTYE4_CH_RX_POLARITY_ADDR 0x11010
#define GTYE4_CH_RX_POLARITY_MSB 0
#define GTYE4_CH_RX_POLARITY_LSB 0
#define GTYE4_CH_RX_POLARITY_MASK BIT_MASK(GTYE4_CH_RX_POLARITY_MSB, GTYE4_CH_RX_POLARITY_LSB)
#define GTYE4_CH_RX_CDR_HOLD_ADDR 0x11020
#define GTYE4_CH_RX_CDR_HOLD_MSB 0
#define GTYE4_CH_RX_CDR_HOLD_LSB 0
#define GTYE4_CH_RX_CDR_HOLD_MASK BIT_MASK(GTYE4_CH_RX_CDR_HOLD_MSB, GTYE4_CH_RX_CDR_HOLD_LSB)
#define GTYE4_CH_RX_CDR_LOCK_ADDR 0x11020
#define GTYE4_CH_RX_CDR_LOCK_MSB 8
#define GTYE4_CH_RX_CDR_LOCK_LSB 8
#define GTYE4_CH_RX_CDR_LOCK_MASK BIT_MASK(GTYE4_CH_RX_CDR_LOCK_MSB, GTYE4_CH_RX_CDR_LOCK_LSB)
#define GTYE4_CH_RX_LPM_EN_ADDR 0x11024
#define GTYE4_CH_RX_LPM_EN_MSB 0
#define GTYE4_CH_RX_LPM_EN_LSB 0
#define GTYE4_CH_RX_LPM_EN_MASK BIT_MASK(GTYE4_CH_RX_LPM_EN_MSB, GTYE4_CH_RX_LPM_EN_LSB)
#define GTYE4_CH_RX_DMONITOR_ADDR 0x11028
#define GTYE4_CH_RX_DMONITOR_MSB 7
#define GTYE4_CH_RX_DMONITOR_LSB 0
#define GTYE4_CH_RX_DMONITOR_MASK BIT_MASK(GTYE4_CH_RX_DMONITOR_MSB, GTYE4_CH_RX_DMONITOR_LSB)
#define GTYE4_CH_RX_PRBS_SEL_ADDR 0x11040
#define GTYE4_CH_RX_PRBS_SEL_MSB 3
#define GTYE4_CH_RX_PRBS_SEL_LSB 0
#define GTYE4_CH_RX_PRBS_SEL_MASK BIT_MASK(GTYE4_CH_RX_PRBS_SEL_MSB, GTYE4_CH_RX_PRBS_SEL_LSB)
#define GTYE4_CH_RX_PRBS_CNT_RESET_ADDR 0x11041
#define GTYE4_CH_RX_PRBS_CNT_RESET_MSB 0
#define GTYE4_CH_RX_PRBS_CNT_RESET_LSB 0
#define GTYE4_CH_RX_PRBS_CNT_RESET_MASK BIT_MASK(GTYE4_CH_RX_PRBS_CNT_RESET_MSB, GTYE4_CH_RX_PRBS_CNT_RESET_LSB)
#define GTYE4_CH_RX_PRBS_LOCKED_ADDR 0x11041
#define GTYE4_CH_RX_PRBS_LOCKED_MSB 8
#define GTYE4_CH_RX_PRBS_LOCKED_LSB 8
#define GTYE4_CH_RX_PRBS_LOCKED_MASK BIT_MASK(GTYE4_CH_RX_PRBS_LOCKED_MSB, GTYE4_CH_RX_PRBS_LOCKED_LSB)
#define GTYE4_CH_RX_PRBS_ERROR_ADDR 0x11041
#define GTYE4_CH_RX_PRBS_ERROR_MSB 9
#define GTYE4_CH_RX_PRBS_ERROR_LSB 9
#define GTYE4_CH_RX_PRBS_ERROR_MASK BIT_MASK(GTYE4_CH_RX_PRBS_ERROR_MSB, GTYE4_CH_RX_PRBS_ERROR_LSB)


def_gt_pll_masked_reg_rw16(gtye4, qpll0_reset, GTYE4_COM_QPLL0_RESET_ADDR, GTYE4_COM_QPLL0_RESET_MASK, GTYE4_COM_QPLL0_RESET_LSB);
int gtye4_pll_qpll0_reset(struct gt_pll *pll);
def_gt_pll_masked_reg_read16(gtye4, qpll0_lock, GTYE4_COM_QPLL0_LOCK_ADDR, GTYE4_COM_QPLL0_LOCK_MASK, GTYE4_COM_QPLL0_LOCK_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll0_pd, GTYE4_COM_QPLL0_PD_ADDR, GTYE4_COM_QPLL0_PD_MASK, GTYE4_COM_QPLL0_PD_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll1_reset, GTYE4_COM_QPLL1_RESET_ADDR, GTYE4_COM_QPLL1_RESET_MASK, GTYE4_COM_QPLL1_RESET_LSB);
int gtye4_pll_qpll1_reset(struct gt_pll *pll);
def_gt_pll_masked_reg_read16(gtye4, qpll1_lock, GTYE4_COM_QPLL1_LOCK_ADDR, GTYE4_COM_QPLL1_LOCK_MASK, GTYE4_COM_QPLL1_LOCK_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll1_pd, GTYE4_COM_QPLL1_PD_ADDR, GTYE4_COM_QPLL1_PD_MASK, GTYE4_COM_QPLL1_PD_LSB);

def_gt_ch_masked_reg_rw16(gtye4, tx_reset, GTYE4_CH_TX_RESET_ADDR, GTYE4_CH_TX_RESET_MASK, GTYE4_CH_TX_RESET_LSB);
int gtye4_ch_tx_reset(struct gt_ch *ch);
def_gt_ch_masked_reg_rw16(gtye4, tx_pma_reset, GTYE4_CH_TX_PMA_RESET_ADDR, GTYE4_CH_TX_PMA_RESET_MASK, GTYE4_CH_TX_PMA_RESET_LSB);
int gtye4_ch_tx_pma_reset(struct gt_ch *ch);
def_gt_ch_masked_reg_rw16(gtye4, tx_pcs_reset, GTYE4_CH_TX_PCS_RESET_ADDR, GTYE4_CH_TX_PCS_RESET_MASK, GTYE4_CH_TX_PCS_RESET_LSB);
int gtye4_ch_tx_pcs_reset(struct gt_ch *ch);
def_gt_ch_masked_reg_read16(gtye4, tx_reset_done, GTYE4_CH_TX_RESET_DONE_ADDR, GTYE4_CH_TX_RESET_DONE_MASK, GTYE4_CH_TX_RESET_DONE_LSB);
def_gt_ch_masked_reg_read16(gtye4, tx_gt_reset_done, GTYE4_CH_TX_GT_RESET_DONE_ADDR, GTYE4_CH_TX_GT_RESET_DONE_MASK, GTYE4_CH_TX_GT_RESET_DONE_LSB);
def_gt_ch_masked_reg_read16(gtye4, tx_pma_reset_done, GTYE4_CH_TX_PMA_RESET_DONE_ADDR, GTYE4_CH_TX_PMA_RESET_DONE_MASK, GTYE4_CH_TX_PMA_RESET_DONE_LSB);
def_gt_ch_masked_reg_read16(gtye4, tx_prgdiv_reset_done, GTYE4_CH_TX_PRGDIV_RESET_DONE_ADDR, GTYE4_CH_TX_PRGDIV_RESET_DONE_MASK, GTYE4_CH_TX_PRGDIV_RESET_DONE_LSB);
def_gt_ch_masked_reg_read16(gtye4, tx_usrclk_act, GTYE4_CH_TX_USRCLK_ACT_ADDR, GTYE4_CH_TX_USRCLK_ACT_MASK, GTYE4_CH_TX_USRCLK_ACT_LSB);
def_gt_ch_masked_reg_rw16(gtye4, tx_pd, GTYE4_CH_TX_PD_ADDR, GTYE4_CH_TX_PD_MASK, GTYE4_CH_TX_PD_LSB);
def_gt_ch_masked_reg_rw16(gtye4, tx_qpll_sel, GTYE4_CH_TX_QPLL_SEL_ADDR, GTYE4_CH_TX_QPLL_SEL_MASK, GTYE4_CH_TX_QPLL_SEL_LSB);
def_gt_ch_masked_reg_rw16(gtye4, tx_polarity, GTYE4_CH_TX_POLARITY_ADDR, GTYE4_CH_TX_POLARITY_MASK, GTYE4_CH_TX_POLARITY_LSB);
def_gt_ch_masked_reg_rw16(gtye4, tx_elecidle, GTYE4_CH_TX_ELECIDLE_ADDR, GTYE4_CH_TX_ELECIDLE_MASK, GTYE4_CH_TX_ELECIDLE_LSB);
def_gt_ch_masked_reg_rw16(gtye4, tx_inhibit, GTYE4_CH_TX_INHIBIT_ADDR, GTYE4_CH_TX_INHIBIT_MASK, GTYE4_CH_TX_INHIBIT_LSB);
def_gt_ch_masked_reg_rw16(gtye4, tx_diffctrl, GTYE4_CH_TX_DIFFCTRL_ADDR, GTYE4_CH_TX_DIFFCTRL_MASK, GTYE4_CH_TX_DIFFCTRL_LSB);
def_gt_ch_masked_reg_rw16(gtye4, tx_maincursor, GTYE4_CH_TX_MAINCURSOR_ADDR, GTYE4_CH_TX_MAINCURSOR_MASK, GTYE4_CH_TX_MAINCURSOR_LSB);
def_gt_ch_masked_reg_rw16(gtye4, tx_precursor, GTYE4_CH_TX_PRECURSOR_ADDR, GTYE4_CH_TX_PRECURSOR_MASK, GTYE4_CH_TX_PRECURSOR_LSB);
def_gt_ch_masked_reg_rw16(gtye4, tx_postcursor, GTYE4_CH_TX_POSTCURSOR_ADDR, GTYE4_CH_TX_POSTCURSOR_MASK, GTYE4_CH_TX_POSTCURSOR_LSB);
def_gt_ch_masked_reg_rw16(gtye4, tx_prbs_sel, GTYE4_CH_TX_PRBS_SEL_ADDR, GTYE4_CH_TX_PRBS_SEL_MASK, GTYE4_CH_TX_PRBS_SEL_LSB);
def_gt_ch_masked_reg_rw16(gtye4, tx_prbs_forcerr, GTYE4_CH_TX_PRBS_FORCERR_ADDR, GTYE4_CH_TX_PRBS_FORCERR_MASK, GTYE4_CH_TX_PRBS_FORCERR_LSB);

def_gt_ch_masked_reg_rw16(gtye4, rx_reset, GTYE4_CH_RX_RESET_ADDR, GTYE4_CH_RX_RESET_MASK, GTYE4_CH_RX_RESET_LSB);
int gtye4_ch_rx_reset(struct gt_ch *ch);
def_gt_ch_masked_reg_rw16(gtye4, rx_pma_reset, GTYE4_CH_RX_PMA_RESET_ADDR, GTYE4_CH_RX_PMA_RESET_MASK, GTYE4_CH_RX_PMA_RESET_LSB);
int gtye4_ch_rx_pma_reset(struct gt_ch *ch);
def_gt_ch_masked_reg_rw16(gtye4, rx_pcs_reset, GTYE4_CH_RX_PCS_RESET_ADDR, GTYE4_CH_RX_PCS_RESET_MASK, GTYE4_CH_RX_PCS_RESET_LSB);
int gtye4_ch_rx_pcs_reset(struct gt_ch *ch);
def_gt_ch_masked_reg_rw16(gtye4, rx_dfe_lpm_reset, GTYE4_CH_RX_DFE_LPM_RESET_ADDR, GTYE4_CH_RX_DFE_LPM_RESET_MASK, GTYE4_CH_RX_DFE_LPM_RESET_LSB);
int gtye4_ch_rx_dfe_lpm_reset(struct gt_ch *ch);
def_gt_ch_masked_reg_rw16(gtye4, eyescan_reset, GTYE4_CH_EYESCAN_RESET_ADDR, GTYE4_CH_EYESCAN_RESET_MASK, GTYE4_CH_EYESCAN_RESET_LSB);
int gtye4_ch_eyescan_reset(struct gt_ch *ch);
def_gt_ch_masked_reg_read16(gtye4, rx_reset_done, GTYE4_CH_RX_RESET_DONE_ADDR, GTYE4_CH_RX_RESET_DONE_MASK, GTYE4_CH_RX_RESET_DONE_LSB);
def_gt_ch_masked_reg_read16(gtye4, rx_gt_reset_done, GTYE4_CH_RX_GT_RESET_DONE_ADDR, GTYE4_CH_RX_GT_RESET_DONE_MASK, GTYE4_CH_RX_GT_RESET_DONE_LSB);
def_gt_ch_masked_reg_read16(gtye4, rx_pma_reset_done, GTYE4_CH_RX_PMA_RESET_DONE_ADDR, GTYE4_CH_RX_PMA_RESET_DONE_MASK, GTYE4_CH_RX_PMA_RESET_DONE_LSB);
def_gt_ch_masked_reg_read16(gtye4, rx_prgdiv_reset_done, GTYE4_CH_RX_PRGDIV_RESET_DONE_ADDR, GTYE4_CH_RX_PRGDIV_RESET_DONE_MASK, GTYE4_CH_RX_PRGDIV_RESET_DONE_LSB);
def_gt_ch_masked_reg_read16(gtye4, rx_usrclk_act, GTYE4_CH_RX_USRCLK_ACT_ADDR, GTYE4_CH_RX_USRCLK_ACT_MASK, GTYE4_CH_RX_USRCLK_ACT_LSB);
def_gt_ch_masked_reg_rw16(gtye4, rx_pd, GTYE4_CH_RX_PD_ADDR, GTYE4_CH_RX_PD_MASK, GTYE4_CH_RX_PD_LSB);
def_gt_ch_masked_reg_rw16(gtye4, rx_qpll_sel, GTYE4_CH_RX_QPLL_SEL_ADDR, GTYE4_CH_RX_QPLL_SEL_MASK, GTYE4_CH_RX_QPLL_SEL_LSB);
def_gt_ch_masked_reg_rw16(gtye4, loopback, GTYE4_CH_LOOPBACK_ADDR, GTYE4_CH_LOOPBACK_MASK, GTYE4_CH_LOOPBACK_LSB);
def_gt_ch_masked_reg_rw16(gtye4, rx_polarity, GTYE4_CH_RX_POLARITY_ADDR, GTYE4_CH_RX_POLARITY_MASK, GTYE4_CH_RX_POLARITY_LSB);
def_gt_ch_masked_reg_rw16(gtye4, rx_cdr_hold, GTYE4_CH_RX_CDR_HOLD_ADDR, GTYE4_CH_RX_CDR_HOLD_MASK, GTYE4_CH_RX_CDR_HOLD_LSB);
def_gt_ch_masked_reg_read16(gtye4, rx_cdr_lock, GTYE4_CH_RX_CDR_LOCK_ADDR, GTYE4_CH_RX_CDR_LOCK_MASK, GTYE4_CH_RX_CDR_LOCK_LSB);
def_gt_ch_masked_reg_rw16(gtye4, rx_lpm_en, GTYE4_CH_RX_LPM_EN_ADDR, GTYE4_CH_RX_LPM_EN_MASK, GTYE4_CH_RX_LPM_EN_LSB);
def_gt_ch_masked_reg_read16(gtye4, rx_dmonitor, GTYE4_CH_RX_DMONITOR_ADDR, GTYE4_CH_RX_DMONITOR_MASK, GTYE4_CH_RX_DMONITOR_LSB);
def_gt_ch_masked_reg_rw16(gtye4, rx_prbs_sel, GTYE4_CH_RX_PRBS_SEL_ADDR, GTYE4_CH_RX_PRBS_SEL_MASK, GTYE4_CH_RX_PRBS_SEL_LSB);
def_gt_ch_masked_reg_rw16(gtye4, rx_prbs_cnt_reset, GTYE4_CH_RX_PRBS_CNT_RESET_ADDR, GTYE4_CH_RX_PRBS_CNT_RESET_MASK, GTYE4_CH_RX_PRBS_CNT_RESET_LSB);
def_gt_ch_masked_reg_read16(gtye4, rx_prbs_locked, GTYE4_CH_RX_PRBS_LOCKED_ADDR, GTYE4_CH_RX_PRBS_LOCKED_MASK, GTYE4_CH_RX_PRBS_LOCKED_LSB);
def_gt_ch_masked_reg_read16(gtye4, rx_prbs_error, GTYE4_CH_RX_PRBS_ERROR_ADDR, GTYE4_CH_RX_PRBS_ERROR_MASK, GTYE4_CH_RX_PRBS_ERROR_LSB);

// common
def_gt_pll_masked_reg_rw16(gtye4, qpll0_cfg0, GTYE4_COM_QPLL0_CFG0_ADDR, GTYE4_COM_QPLL0_CFG0_MASK, GTYE4_COM_QPLL0_CFG0_LSB);
def_gt_pll_masked_reg_rw16(gtye4, common_cfg0, GTYE4_COM_COMMON_CFG0_ADDR, GTYE4_COM_COMMON_CFG0_MASK, GTYE4_COM_COMMON_CFG0_LSB);
def_gt_pll_masked_reg_rw16(gtye4, ppf0_cfg, GTYE4_COM_PPF0_CFG_ADDR, GTYE4_COM_PPF0_CFG_MASK, GTYE4_COM_PPF0_CFG_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll0clkout_rate, GTYE4_COM_QPLL0CLKOUT_RATE_ADDR, GTYE4_COM_QPLL0CLKOUT_RATE_MASK, GTYE4_COM_QPLL0CLKOUT_RATE_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll0_cfg1, GTYE4_COM_QPLL0_CFG1_ADDR, GTYE4_COM_QPLL0_CFG1_MASK, GTYE4_COM_QPLL0_CFG1_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll0_cfg2, GTYE4_COM_QPLL0_CFG2_ADDR, GTYE4_COM_QPLL0_CFG2_MASK, GTYE4_COM_QPLL0_CFG2_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll0_lock_cfg, GTYE4_COM_QPLL0_LOCK_CFG_ADDR, GTYE4_COM_QPLL0_LOCK_CFG_MASK, GTYE4_COM_QPLL0_LOCK_CFG_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll0_init_cfg0, GTYE4_COM_QPLL0_INIT_CFG0_ADDR, GTYE4_COM_QPLL0_INIT_CFG0_MASK, GTYE4_COM_QPLL0_INIT_CFG0_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll0_init_cfg1, GTYE4_COM_QPLL0_INIT_CFG1_ADDR, GTYE4_COM_QPLL0_INIT_CFG1_MASK, GTYE4_COM_QPLL0_INIT_CFG1_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll0_fbdiv, GTYE4_COM_QPLL0_FBDIV_ADDR, GTYE4_COM_QPLL0_FBDIV_MASK, GTYE4_COM_QPLL0_FBDIV_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll0_cfg3, GTYE4_COM_QPLL0_CFG3_ADDR, GTYE4_COM_QPLL0_CFG3_MASK, GTYE4_COM_QPLL0_CFG3_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll0_cp, GTYE4_COM_QPLL0_CP_ADDR, GTYE4_COM_QPLL0_CP_MASK, GTYE4_COM_QPLL0_CP_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll0_refclk_div, GTYE4_COM_QPLL0_REFCLK_DIV_ADDR, GTYE4_COM_QPLL0_REFCLK_DIV_MASK, GTYE4_COM_QPLL0_REFCLK_DIV_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll0_ips_refclk_sel, GTYE4_COM_QPLL0_IPS_REFCLK_SEL_ADDR, GTYE4_COM_QPLL0_IPS_REFCLK_SEL_MASK, GTYE4_COM_QPLL0_IPS_REFCLK_SEL_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll0_ips_en, GTYE4_COM_QPLL0_IPS_EN_ADDR, GTYE4_COM_QPLL0_IPS_EN_MASK, GTYE4_COM_QPLL0_IPS_EN_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll0_lpf, GTYE4_COM_QPLL0_LPF_ADDR, GTYE4_COM_QPLL0_LPF_MASK, GTYE4_COM_QPLL0_LPF_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll0_cfg1_g3, GTYE4_COM_QPLL0_CFG1_G3_ADDR, GTYE4_COM_QPLL0_CFG1_G3_MASK, GTYE4_COM_QPLL0_CFG1_G3_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll0_cfg2_g3, GTYE4_COM_QPLL0_CFG2_G3_ADDR, GTYE4_COM_QPLL0_CFG2_G3_MASK, GTYE4_COM_QPLL0_CFG2_G3_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll0_lpf_g3, GTYE4_COM_QPLL0_LPF_G3_ADDR, GTYE4_COM_QPLL0_LPF_G3_MASK, GTYE4_COM_QPLL0_LPF_G3_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll0_lock_cfg_g3, GTYE4_COM_QPLL0_LOCK_CFG_G3_ADDR, GTYE4_COM_QPLL0_LOCK_CFG_G3_MASK, GTYE4_COM_QPLL0_LOCK_CFG_G3_LSB);
def_gt_pll_masked_reg_rw16(gtye4, rsvd_attr0, GTYE4_COM_RSVD_ATTR0_ADDR, GTYE4_COM_RSVD_ATTR0_MASK, GTYE4_COM_RSVD_ATTR0_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll0_fbdiv_g3, GTYE4_COM_QPLL0_FBDIV_G3_ADDR, GTYE4_COM_QPLL0_FBDIV_G3_MASK, GTYE4_COM_QPLL0_FBDIV_G3_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll0_rate_sw_use_drp, GTYE4_COM_QPLL0_RATE_SW_USE_DRP_ADDR, GTYE4_COM_QPLL0_RATE_SW_USE_DRP_MASK, GTYE4_COM_QPLL0_RATE_SW_USE_DRP_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll0_pcie_en, GTYE4_COM_QPLL0_PCIE_EN_ADDR, GTYE4_COM_QPLL0_PCIE_EN_MASK, GTYE4_COM_QPLL0_PCIE_EN_LSB);
def_gt_pll_masked_reg_rw16(gtye4, rxrecclkout0_sel, GTYE4_COM_RXRECCLKOUT0_SEL_ADDR, GTYE4_COM_RXRECCLKOUT0_SEL_MASK, GTYE4_COM_RXRECCLKOUT0_SEL_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll0_sdm_cfg0, GTYE4_COM_QPLL0_SDM_CFG0_ADDR, GTYE4_COM_QPLL0_SDM_CFG0_MASK, GTYE4_COM_QPLL0_SDM_CFG0_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll0_sdm_cfg1, GTYE4_COM_QPLL0_SDM_CFG1_ADDR, GTYE4_COM_QPLL0_SDM_CFG1_MASK, GTYE4_COM_QPLL0_SDM_CFG1_LSB);
def_gt_pll_masked_reg_rw16(gtye4, sdm0initseed0_0, GTYE4_COM_SDM0INITSEED0_0_ADDR, GTYE4_COM_SDM0INITSEED0_0_MASK, GTYE4_COM_SDM0INITSEED0_0_LSB);
def_gt_pll_masked_reg_rw16(gtye4, sdm0initseed0_1, GTYE4_COM_SDM0INITSEED0_1_ADDR, GTYE4_COM_SDM0INITSEED0_1_MASK, GTYE4_COM_SDM0INITSEED0_1_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll0_sdm_cfg2, GTYE4_COM_QPLL0_SDM_CFG2_ADDR, GTYE4_COM_QPLL0_SDM_CFG2_MASK, GTYE4_COM_QPLL0_SDM_CFG2_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll0_cp_g3, GTYE4_COM_QPLL0_CP_G3_ADDR, GTYE4_COM_QPLL0_CP_G3_MASK, GTYE4_COM_QPLL0_CP_G3_LSB);
def_gt_pll_masked_reg_rw16(gtye4, rsvd_attr1, GTYE4_COM_RSVD_ATTR1_ADDR, GTYE4_COM_RSVD_ATTR1_MASK, GTYE4_COM_RSVD_ATTR1_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll0_cfg4, GTYE4_COM_QPLL0_CFG4_ADDR, GTYE4_COM_QPLL0_CFG4_MASK, GTYE4_COM_QPLL0_CFG4_LSB);
def_gt_pll_masked_reg_rw16(gtye4, ub_cfg0, GTYE4_COM_UB_CFG0_ADDR, GTYE4_COM_UB_CFG0_MASK, GTYE4_COM_UB_CFG0_LSB);
def_gt_pll_masked_reg_rw16(gtye4, ub_cfg1, GTYE4_COM_UB_CFG1_ADDR, GTYE4_COM_UB_CFG1_MASK, GTYE4_COM_UB_CFG1_LSB);
def_gt_pll_masked_reg_rw16(gtye4, ub_cfg2, GTYE4_COM_UB_CFG2_ADDR, GTYE4_COM_UB_CFG2_MASK, GTYE4_COM_UB_CFG2_LSB);
def_gt_pll_masked_reg_rw16(gtye4, ub_cfg3, GTYE4_COM_UB_CFG3_ADDR, GTYE4_COM_UB_CFG3_MASK, GTYE4_COM_UB_CFG3_LSB);
def_gt_pll_masked_reg_rw16(gtye4, ub_cfg4, GTYE4_COM_UB_CFG4_ADDR, GTYE4_COM_UB_CFG4_MASK, GTYE4_COM_UB_CFG4_LSB);
def_gt_pll_masked_reg_rw16(gtye4, ub_cfg5, GTYE4_COM_UB_CFG5_ADDR, GTYE4_COM_UB_CFG5_MASK, GTYE4_COM_UB_CFG5_LSB);
def_gt_pll_masked_reg_rw16(gtye4, ub_cfg6, GTYE4_COM_UB_CFG6_ADDR, GTYE4_COM_UB_CFG6_MASK, GTYE4_COM_UB_CFG6_LSB);
def_gt_pll_masked_reg_rw16(gtye4, bias_cfg0, GTYE4_COM_BIAS_CFG0_ADDR, GTYE4_COM_BIAS_CFG0_MASK, GTYE4_COM_BIAS_CFG0_LSB);
def_gt_pll_masked_reg_rw16(gtye4, bias_cfg1, GTYE4_COM_BIAS_CFG1_ADDR, GTYE4_COM_BIAS_CFG1_MASK, GTYE4_COM_BIAS_CFG1_LSB);
def_gt_pll_masked_reg_rw16(gtye4, bias_cfg2, GTYE4_COM_BIAS_CFG2_ADDR, GTYE4_COM_BIAS_CFG2_MASK, GTYE4_COM_BIAS_CFG2_LSB);
def_gt_pll_masked_reg_rw16(gtye4, bias_cfg3, GTYE4_COM_BIAS_CFG3_ADDR, GTYE4_COM_BIAS_CFG3_MASK, GTYE4_COM_BIAS_CFG3_LSB);
def_gt_pll_masked_reg_rw16(gtye4, bias_cfg4, GTYE4_COM_BIAS_CFG4_ADDR, GTYE4_COM_BIAS_CFG4_MASK, GTYE4_COM_BIAS_CFG4_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll1_cfg0, GTYE4_COM_QPLL1_CFG0_ADDR, GTYE4_COM_QPLL1_CFG0_MASK, GTYE4_COM_QPLL1_CFG0_LSB);
def_gt_pll_masked_reg_rw16(gtye4, common_cfg1, GTYE4_COM_COMMON_CFG1_ADDR, GTYE4_COM_COMMON_CFG1_MASK, GTYE4_COM_COMMON_CFG1_LSB);
def_gt_pll_masked_reg_rw16(gtye4, por_cfg, GTYE4_COM_POR_CFG_ADDR, GTYE4_COM_POR_CFG_MASK, GTYE4_COM_POR_CFG_LSB);
def_gt_pll_masked_reg_rw16(gtye4, ppf1_cfg, GTYE4_COM_PPF1_CFG_ADDR, GTYE4_COM_PPF1_CFG_MASK, GTYE4_COM_PPF1_CFG_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll1clkout_rate, GTYE4_COM_QPLL1CLKOUT_RATE_ADDR, GTYE4_COM_QPLL1CLKOUT_RATE_MASK, GTYE4_COM_QPLL1CLKOUT_RATE_LSB);
def_gt_pll_masked_reg_rw16(gtye4, bias_cfg_rsvd, GTYE4_COM_BIAS_CFG_RSVD_ADDR, GTYE4_COM_BIAS_CFG_RSVD_MASK, GTYE4_COM_BIAS_CFG_RSVD_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll1_cfg1, GTYE4_COM_QPLL1_CFG1_ADDR, GTYE4_COM_QPLL1_CFG1_MASK, GTYE4_COM_QPLL1_CFG1_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll1_cfg2, GTYE4_COM_QPLL1_CFG2_ADDR, GTYE4_COM_QPLL1_CFG2_MASK, GTYE4_COM_QPLL1_CFG2_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll1_lock_cfg, GTYE4_COM_QPLL1_LOCK_CFG_ADDR, GTYE4_COM_QPLL1_LOCK_CFG_MASK, GTYE4_COM_QPLL1_LOCK_CFG_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll1_init_cfg0, GTYE4_COM_QPLL1_INIT_CFG0_ADDR, GTYE4_COM_QPLL1_INIT_CFG0_MASK, GTYE4_COM_QPLL1_INIT_CFG0_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll1_init_cfg1, GTYE4_COM_QPLL1_INIT_CFG1_ADDR, GTYE4_COM_QPLL1_INIT_CFG1_MASK, GTYE4_COM_QPLL1_INIT_CFG1_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll1_fbdiv, GTYE4_COM_QPLL1_FBDIV_ADDR, GTYE4_COM_QPLL1_FBDIV_MASK, GTYE4_COM_QPLL1_FBDIV_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll1_cfg3, GTYE4_COM_QPLL1_CFG3_ADDR, GTYE4_COM_QPLL1_CFG3_MASK, GTYE4_COM_QPLL1_CFG3_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll1_cp, GTYE4_COM_QPLL1_CP_ADDR, GTYE4_COM_QPLL1_CP_MASK, GTYE4_COM_QPLL1_CP_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll1_refclk_div, GTYE4_COM_QPLL1_REFCLK_DIV_ADDR, GTYE4_COM_QPLL1_REFCLK_DIV_MASK, GTYE4_COM_QPLL1_REFCLK_DIV_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll1_ips_refclk_sel, GTYE4_COM_QPLL1_IPS_REFCLK_SEL_ADDR, GTYE4_COM_QPLL1_IPS_REFCLK_SEL_MASK, GTYE4_COM_QPLL1_IPS_REFCLK_SEL_LSB);
def_gt_pll_masked_reg_rw16(gtye4, sarc_en, GTYE4_COM_SARC_EN_ADDR, GTYE4_COM_SARC_EN_MASK, GTYE4_COM_SARC_EN_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll1_ips_en, GTYE4_COM_QPLL1_IPS_EN_ADDR, GTYE4_COM_QPLL1_IPS_EN_MASK, GTYE4_COM_QPLL1_IPS_EN_LSB);
def_gt_pll_masked_reg_rw16(gtye4, sarc_sel, GTYE4_COM_SARC_SEL_ADDR, GTYE4_COM_SARC_SEL_MASK, GTYE4_COM_SARC_SEL_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll1_lpf, GTYE4_COM_QPLL1_LPF_ADDR, GTYE4_COM_QPLL1_LPF_MASK, GTYE4_COM_QPLL1_LPF_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll1_cfg1_g3, GTYE4_COM_QPLL1_CFG1_G3_ADDR, GTYE4_COM_QPLL1_CFG1_G3_MASK, GTYE4_COM_QPLL1_CFG1_G3_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll1_cfg2_g3, GTYE4_COM_QPLL1_CFG2_G3_ADDR, GTYE4_COM_QPLL1_CFG2_G3_MASK, GTYE4_COM_QPLL1_CFG2_G3_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll1_lpf_g3, GTYE4_COM_QPLL1_LPF_G3_ADDR, GTYE4_COM_QPLL1_LPF_G3_MASK, GTYE4_COM_QPLL1_LPF_G3_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll1_lock_cfg_g3, GTYE4_COM_QPLL1_LOCK_CFG_G3_ADDR, GTYE4_COM_QPLL1_LOCK_CFG_G3_MASK, GTYE4_COM_QPLL1_LOCK_CFG_G3_LSB);
def_gt_pll_masked_reg_rw16(gtye4, rsvd_attr2, GTYE4_COM_RSVD_ATTR2_ADDR, GTYE4_COM_RSVD_ATTR2_MASK, GTYE4_COM_RSVD_ATTR2_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll1_fbdiv_g3, GTYE4_COM_QPLL1_FBDIV_G3_ADDR, GTYE4_COM_QPLL1_FBDIV_G3_MASK, GTYE4_COM_QPLL1_FBDIV_G3_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll1_rate_sw_use_drp, GTYE4_COM_QPLL1_RATE_SW_USE_DRP_ADDR, GTYE4_COM_QPLL1_RATE_SW_USE_DRP_MASK, GTYE4_COM_QPLL1_RATE_SW_USE_DRP_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll1_pci_en, GTYE4_COM_QPLL1_PCI_EN_ADDR, GTYE4_COM_QPLL1_PCI_EN_MASK, GTYE4_COM_QPLL1_PCI_EN_LSB);
def_gt_pll_masked_reg_rw16(gtye4, rxrecclkout1_sel, GTYE4_COM_RXRECCLKOUT1_SEL_ADDR, GTYE4_COM_RXRECCLKOUT1_SEL_MASK, GTYE4_COM_RXRECCLKOUT1_SEL_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll1_sdm_cfg0, GTYE4_COM_QPLL1_SDM_CFG0_ADDR, GTYE4_COM_QPLL1_SDM_CFG0_MASK, GTYE4_COM_QPLL1_SDM_CFG0_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll1_sdm_cfg1, GTYE4_COM_QPLL1_SDM_CFG1_ADDR, GTYE4_COM_QPLL1_SDM_CFG1_MASK, GTYE4_COM_QPLL1_SDM_CFG1_LSB);
def_gt_pll_masked_reg_rw16(gtye4, sdm1initseed0_0, GTYE4_COM_SDM1INITSEED0_0_ADDR, GTYE4_COM_SDM1INITSEED0_0_MASK, GTYE4_COM_SDM1INITSEED0_0_LSB);
def_gt_pll_masked_reg_rw16(gtye4, sdm1initseed0_1, GTYE4_COM_SDM1INITSEED0_1_ADDR, GTYE4_COM_SDM1INITSEED0_1_MASK, GTYE4_COM_SDM1INITSEED0_1_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll1_sdm_cfg2, GTYE4_COM_QPLL1_SDM_CFG2_ADDR, GTYE4_COM_QPLL1_SDM_CFG2_MASK, GTYE4_COM_QPLL1_SDM_CFG2_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll1_cp_g3, GTYE4_COM_QPLL1_CP_G3_ADDR, GTYE4_COM_QPLL1_CP_G3_MASK, GTYE4_COM_QPLL1_CP_G3_LSB);
def_gt_pll_masked_reg_rw16(gtye4, rsvd_attr3, GTYE4_COM_RSVD_ATTR3_ADDR, GTYE4_COM_RSVD_ATTR3_MASK, GTYE4_COM_RSVD_ATTR3_LSB);
def_gt_pll_masked_reg_rw16(gtye4, qpll1_cfg4, GTYE4_COM_QPLL1_CFG4_ADDR, GTYE4_COM_QPLL1_CFG4_MASK, GTYE4_COM_QPLL1_CFG4_LSB);

// RX
def_gt_ch_masked_reg_rw16(gtye4, rx_data_width_raw, GTYE4_CH_RX_DATA_WIDTH_ADDR, GTYE4_CH_RX_DATA_WIDTH_MASK, GTYE4_CH_RX_DATA_WIDTH_LSB);
int gtye4_ch_get_rx_data_width(struct gt_ch *ch, uint32_t *val);

def_gt_ch_masked_reg_rw16(gtye4, rx_int_data_width_raw, GTYE4_CH_RX_INT_DATAWIDTH_ADDR, GTYE4_CH_RX_INT_DATAWIDTH_MASK, GTYE4_CH_RX_INT_DATAWIDTH_LSB);
int gtye4_ch_get_rx_int_data_width(struct gt_ch *ch, uint32_t *val);

def_gt_ch_masked_reg_rw16(gtye4, es_prescale, GTYE4_CH_ES_PRESCALE_ADDR, GTYE4_CH_ES_PRESCALE_MASK, GTYE4_CH_ES_PRESCALE_LSB);
def_gt_ch_masked_reg_rw16(gtye4, es_eye_scan_en, GTYE4_CH_ES_EYE_SCAN_EN_ADDR, GTYE4_CH_ES_EYE_SCAN_EN_MASK, GTYE4_CH_ES_EYE_SCAN_EN_LSB);
def_gt_ch_masked_reg_rw16(gtye4, es_errdet_en, GTYE4_CH_ES_ERRDET_EN_ADDR, GTYE4_CH_ES_ERRDET_EN_MASK, GTYE4_CH_ES_ERRDET_EN_LSB);
def_gt_ch_masked_reg_rw16(gtye4, es_control, GTYE4_CH_ES_CONTROL_ADDR, GTYE4_CH_ES_CONTROL_MASK, GTYE4_CH_ES_CONTROL_LSB);

int gtye4_ch_set_es_qual_mask(struct gt_ch *ch, uint8_t *mask);
int gtye4_ch_set_es_qual_mask_clear(struct gt_ch *ch);

int gtye4_ch_set_es_sdata_mask(struct gt_ch *ch, uint8_t *mask);
int gtye4_ch_set_es_sdata_mask_width(struct gt_ch *ch, int width);

def_gt_ch_masked_reg_rw16(gtye4, es_horz_offset, GTYE4_CH_ES_HORZ_OFFSET_ADDR, GTYE4_CH_ES_HORZ_OFFSET_MASK, GTYE4_CH_ES_HORZ_OFFSET_LSB);
def_gt_ch_masked_reg_rw16(gtye4, rx_eyescan_vs_range, GTYE4_CH_RX_EYESCAN_VS_RANGE_ADDR, GTYE4_CH_RX_EYESCAN_VS_RANGE_MASK, GTYE4_CH_RX_EYESCAN_VS_RANGE_LSB);
def_gt_ch_masked_reg_rw16(gtye4, rx_eyescan_vs_code, GTYE4_CH_RX_EYESCAN_VS_CODE_ADDR, GTYE4_CH_RX_EYESCAN_VS_CODE_MASK, GTYE4_CH_RX_EYESCAN_VS_CODE_LSB);
def_gt_ch_masked_reg_rw16(gtye4, rx_eyescan_vs_ut_sign, GTYE4_CH_RX_EYESCAN_VS_UT_SIGN_ADDR, GTYE4_CH_RX_EYESCAN_VS_UT_SIGN_MASK, GTYE4_CH_RX_EYESCAN_VS_UT_SIGN_LSB);
def_gt_ch_masked_reg_rw16(gtye4, rx_eyescan_vs_neg_dir, GTYE4_CH_RX_EYESCAN_VS_NEG_DIR_ADDR, GTYE4_CH_RX_EYESCAN_VS_NEG_DIR_MASK, GTYE4_CH_RX_EYESCAN_VS_NEG_DIR_LSB);
def_gt_ch_masked_reg_read16(gtye4, es_error_count, GTYE4_CH_ES_ERROR_COUNT_ADDR, GTYE4_CH_ES_ERROR_COUNT_MASK, GTYE4_CH_ES_ERROR_COUNT_LSB);
def_gt_ch_masked_reg_read16(gtye4, es_sample_count, GTYE4_CH_ES_SAMPLE_COUNT_ADDR, GTYE4_CH_ES_SAMPLE_COUNT_MASK, GTYE4_CH_ES_SAMPLE_COUNT_LSB);
def_gt_ch_masked_reg_read16(gtye4, es_control_status, GTYE4_CH_ES_CONTROL_STATUS_ADDR, GTYE4_CH_ES_CONTROL_STATUS_MASK, GTYE4_CH_ES_CONTROL_STATUS_LSB);

int gtye4_ch_get_rx_prbs_error_count(struct gt_ch *ch, uint32_t *val);

// TX
def_gt_ch_masked_reg_rw16(gtye4, tx_data_width_raw, GTYE4_CH_TX_DATA_WIDTH_ADDR, GTYE4_CH_TX_DATA_WIDTH_MASK, GTYE4_CH_TX_DATA_WIDTH_LSB);
int gtye4_ch_get_tx_data_width(struct gt_ch *ch, uint32_t *val);

def_gt_ch_masked_reg_rw16(gtye4, tx_int_data_width_raw, GTYE4_CH_TX_INT_DATAWIDTH_ADDR, GTYE4_CH_TX_INT_DATAWIDTH_MASK, GTYE4_CH_TX_INT_DATAWIDTH_LSB);
int gtye4_ch_get_tx_int_data_width(struct gt_ch *ch, uint32_t *val);

extern const struct gt_quad_ops gtye4_gt_quad_ops;

#endif /* XCVR_GTYE4_H */
